Press Releases

Enea Extends its Optima Tools to Support Heterogeneous Multicore and Linux

One Development Suite Covers both CPUs and DSPs for RTOS as well as Linux Applications

STOCKHOLM, Sweden, May 3, 2011 – Enea (NASDAQ OMX Nordic:ENEA) today announced extended support in its Eclipse-based integrated development environment (IDE) Enea® Optima (www.enea.com/optima) for heterogeneous multicore systems-on-chips (SoC) with both CPU and DSP processor architectures. In addition to the profiling, log and debug capabilities for the Enea OSE® RTOS on both CPUs and DSPs, Optima now also supports the Linux operating system with C/C++ application debug functionality and visualization and analysis tools that integrate with the familiar Linux LTTng tracing framework.

“Software complexity is growing rapidly with the introduction of highly integrated heterogeneous SoC solutions,“ said Marcus Hjortsberg, vice president marketing at Enea. “To accelerate development schedules developers need an integrated tool chain that offers full system visualization and debug capabilities across CPU and DSP cores and a mix of different operating systems including OSE and Linux“.

Optima is a suite of system and application development tools originally designed for the OSE realtime operating system that allows users not only to write, debug and optimize C/C++ applications, but also to analyze and optimize system wide behavior. As the only operating system that supports both CPU and DSP architectures, OSE provides a unified programming model and API for heterogeneous SoC multicore processors. Developers using OSE and Linux can now benefit from using a single tool, Optima, to simultaneously debug and visualize software on both CPUs and DSPs as part of a heterogeneous SoC, removing the need for multiple different tools with different capabilities depending on whether developing software for the CPU, the DSP, for an RTOS or Linux.

“Optima reflects Enea’s deep understanding of the embedded software design challenges and opportunities that heterogeneous multicore devices present,“ said Scott Aylor, director and general manager of Freescale’s Wireless Access Division. “We look forward to working with Enea to make Optima available for the innovative QorIQ Qonverge platform, which combines Freescale’s leading Power Architecture MPU and StarCore DSP technologies in a single SoC”.

With the introduction of DSP support in the Optima System Profiler, all of the Optima system visualization, optimization and analysis tools are now available for both CPUs and DSPs. The System Profiler allows developers to capture, visualize and analyze statistics such as processor usage for a certain core, a certain program, or a certain software thread, as well as statistics from application or hardware level counters.

Since Optima integrates seamlessly with Eclipse-based tools from hardware vendors, such as CodeWarrior from Freescale or Code Composer Studio from Texas Instruments, the DSP-specific compilation and C/C++ debug tools and the standard Optima tools are all available within the same integrated development environment, providing an end to end software development solution for heterogeneous multicore devices.

For applications where criteria such as the breadth of the ecosystem and availability of specific application or driver software is more important than strict realtime properties, Linux is often the natural OS choice for the CPU part of a heterogeneous CPU / DSP device. To support such configurations, the Optima suite of tools has now been extended with C/C++ debug functionality for Linux applications and with support for the familiar Linux LTTng tracing framework. Since LTTng is a standard part of the Linux kernel and included in most embedded Linux distributions, Linux developers can now take full advantage of the powerful visualization and analysis features of the Optima Log Analyzer. This includes sequence chart presentation of process interaction and I/O, Gantt chart presentation of thread execution, as well as log information merge, compare, search and assertion facilities that radically reduce the time required for failure and test result analysis.