Enea OSEck (OSE Compact Kernel) is a DSP-optimized version of the Enea OSE RTOS, suitable for high performance, memory constrained applications.
Built on a compact kernel with an extremely small memory footprint, OSEck brings rich functionality, high performance, and true real-time behavior for single and multicore devices.
Ideal for time-critical signal processing
The event-driven, pre-emptive performance of OSEck is ideal for time-critical signal processing and control applications. The intuitive message passing architecture and programming model facilitates modular system design and reduces complexity.
OSEck features system-level simulation so that code development can be made in advance of target hardware.
The DSPNet + Open SSL network and security features secure networking through IPv4/IPv6 stack, IPSEC and SSH, with a modular design optimized for small footprint and high performance.
Powerful yet Easy to Use
OSEck provides a subset of the OSE API, making it easy to migrate applications between OSE and OSEck, with a minimum of changes to the application code.
OSEck is ideal for applications with tight memory constraints that require reliable real-time control and signal processing. It is:
- Designed expressly for distributed heterogeneous environments
- Highly portable; optimized for single- and multicore DSPs
- Scalable at the function level, allowing functionality and footprint can be optimized for each application.
Save time integrating OSEck enabled DSPs with Enea Linux
Thanks to the built in high performance IPC, integrating DSP cores running OSEck with a Linux CPU over media such as shared memory, sRIO or Ethernet using Enea LINX becomes a breeze.
Enea dSPEED and Linux Remote Command based on LINX together with OSEck connects management and debug to DSPs from Linux hosts enabling fast development of robust DSP platforms in even the most advanced multicore SoC and multi SoC LTE Advanced and IMS media gateway systems.
The Packet Flow Layer (PFL) implements a minimal networking/IP-stack for packets and (unfragmented) datagrams. Packet reception and transmission is performed on flows (conceptually similar to connected datagram sockets). Flows are bi-directional, packets can both be received from the flow and transmitted onto the flow. UDP/IP is the standardprotocol but certain custom protocols are also supported.
PFL relies on hardware offload for the necessary packet classification, but suitable software emulation could make PFL useful on architectures that lack the required hardware packet classification.
Texas Instruments KeyStone II including:
TCI663x (e.g. TCI6636/38)
Texas Instruments C6000 and C5000 families including:
TMS320C66x (e.g. C6670/78)
TMS320C64x+ (e.g. C6455/72/74/82/84/86/87/88)
B4-series (e.g. B4860/4420)
MSC815x (e.g. MSC8156/57)
ZSP400 and DSP cores